A liquid crystal display (LCD) has become a mainstream product among the current flat panel display devices due to its characteristics of small size, low power consumption, no radiation, etc.
Currently, a more common liquid crystal display is a liquid crystal display of twisted nematic (TN) display mode. With the development of display technology, a liquid crystal display of advanced super dimension switch (ADS) display mode also appears. Nowadays, a thin film transistor-liquid crystal display (TFT-LCD) is more mature technically. A liquid crystal display includes an array substrate and a color-filter substrate, wherein thin film transistors are formed on the array substrate, each of the thin film transistors includes a gate electrode, a source electrode and a drain electrode, and is commonly formed of an amorphous silicon (a-Si) material.
With the development of display technology, a manner in which a thin film transistor is formed of a polysilicon (p-Si) material appears. Specifically, an active region is formed first by using a polysilicon (p-Si) material, then crystallization and ion implantation are performed on the active region, thus a source electrode and a drain electrode of the thin film transistor are formed. Researches have disclosed that the performance of a thin film transistor formed of a polysilicon (p-Si) material is higher than that of a thin film transistor formed of an amorphous silicon material by more than 100 times. A polysilicon includes a high-temperature polysilicon and a low-temperature polysilicon. A thin film transistor formed of a low-temperature polysilicon not only has a high electron mobility but also can has a reduced size. Thus, the thin film transistor formed of a low-temperature polysilicon is widely used in an array substrate, thereby not only a high aperture ratio is realized but also the corresponding display device has advantages of high brightness and low power consumption.
Compared with a thin film transistor formed of an amorphous silicon material, a thin film transistor formed of a low-temperature polysilicon has a larger leakage current when it operates. Thus, in order to reduce the leakage current, as shown by a schematic diagram of the structure of the array substrate in FIG. 1, light shielding metal layers 3 are disposed such that they are on the array substrate 1 and under the active region 4 corresponding to the thin film transistor. The light shielding metal layers 3 shield a part of light which irradiates to an area between a drain electrode 7 and a source electrode 6, thus the leakage current is reduced. Alternatively, the leakage current can be reduced to some extent by arranging a lightly doped drain 8 in the active region 4 with an ion implantation method (also known as an ion doping method) during forming the drain electrode 7 and the source electrode 6, by configuring the thin film transistor to have a double-gate structure (e.g. to have two gate electrodes 5 as shown in FIG. 1), or by other ways.
Compared with the array substrate comprising the thin film transistors formed of amorphous silicon material, the array substrate comprising the thin film transistors formed of polysilicon material requires a plurality of patterning processes when being manufactured. As shown in the diagrams of manufacturing steps (steps P1-P10) for the array substrate in FIGS. 2a to 2j, in order to form the light shielding metal layer 3 for reducing the leakage current of the thin film transistor, a patterning process including an exposure process (e.g., the step P1) for the light shielding metal layer 3 must be added when the array substrate is manufactured. The patterning process including an exposure process for the light shielding metal layer 3 together with the patterning processes of other layers during manufacturing the array substrate cause the number of patterning processes of a method for manufacturing the array substrate with a polysilicon material to increase, cause the manufacturing processes of the corresponding array substrate to be complex and numerous, and cause the manufacturing efficiency of the corresponding array substrate to be low. Said patterning processes of other layers during manufacturing the array substrate include, for example, a patterning process for manufacturing a data line 2 (e.g., the step P6), a patterning process for manufacturing a common electrode 12 (e.g., the step P8), a patterning process for manufacturing a pixel electrode 14 (e.g., the step P10), a patterning process for manufacturing a first via 15 which forms the electrical connection between the data line 2 and the source electrode 6 in a gate insulating layer 10 and an intermediate dielectric layer 11 (e.g., the step P5), a patterning process for manufacturing a third via 17 which forms the electrical connection between the pixel electrode 14 and the drain electrode 7 in the gate insulating layer 10 and the intermediate dielectric layer 11, a patterning process for manufacturing a fourth via 18 in a passivation layer 13, and a patterning process for manufacturing a fifth via 19 in a flat layer 20 (as shown in steps P5, P7 and P9, wherein the data line 2 and the common electrode 12 must be insulated from each other while the data line 2 and the common electrode 12 overlap or intercross in an orthogonal projection direction, thus the flat layer 20 playing an insulating role therebetween is necessary; correspondingly, the patterning process for forming the fifth via 19 which forms the electrical connection between the pixel electrode 14 and the drain electrode 7 in the flat layer 20 is necessary). A patterning process for manufacturing a buffer layer 9 and the active region 4 (step P2) as shown in FIG. 2b, a patterning process for manufacturing the gate insulating layer 10 and the gate electrodes 5 (step P3) as shown in FIG. 2c, a patterning process for manufacturing the source electrode 6, the drain electrode 7, and the lightly doped drain 8 (step P4) as shown in FIG. 2d, and the like are the same as the corresponding patterning processes described in detail below. The same reference number denotes the same element throughout the present description.